The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor structure including an embedded stressor element that includes a delta monolayer of a dopant located an upper surface thereof. The present invention also provides a method of fabricating such a semiconductor structure.
Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance such as, for example, drive current. For example, in common silicon technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel region of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded SiGe or Si:C stressors (i.e., stress wells) within the source and drain regions of a complementary metal oxide semiconductor (CMOS) device to induce compressive or tensile strain in the channel region located between the source region and the drain region. For example, it has been demonstrated that hole mobility can be enhanced significantly in p-channel silicon transistors by using an embedded SiGe stressor in the source and drain regions. For re-channel silicon transistors, it has also been demonstrated that the electron mobility can be enhanced by using selective Si:C in which C is substitutional.
Although prior art structures including embedded stressor elements are known in the art, there is still a need for forming semiconductor structures, including CMOS structures, which limit the series contact resistance to the channel resistance. This requirement needs not only extremely low junction sheet resistance, but also ultra low-contact resistivites that can be obtained with existing self-aligned silicidation technology.